The present invention relates to a sequence generator for generating sequences of values.
In an increasing number of technical fields, the transmission and processing of analog signals is successively being replaced by transmission and processing of digitally represented signals or data. Digital transmission or processing of data provides advantages as compared to an analog transmission or processing of signals, especially with the availability of cheap computing power, required for an efficient handling of digital data.
A trend towards digitalization is also evident in telecommunications systems, where an analog handling of data is successively being replaced by digital representation, processing and transmission of data.
For example, a CDMA (code division multiple access) telecommunications system may be mostly digital, i.e., it can represent, process and transmit voice signals, user data and control data within the system in a digital form.
In a CDMA system a plurality of different communication channels is combined to form a single signal to be transmitted to a receiving station. At the receiving station each of the plurality of communication channels is recovered from the transmitted signal. However, to be able to do so, before combining the communication channels, data of each communication channel need to be digitally marked in order to be able to distinguish the individual channels after reception at the receiving station. This processing of data of a communication channel may include spreading the narrow banded signal of each particular communication channel into a wide band signal using a shortcode.
A shortcode is a defined sequence of bits or chips, which is preferably orthogonal to other shortcodes. Spreading of communication channel data may be achieved by representing each single bit-value of channel data by the shortcode or the inverted shortcode, respectively. For example, each logical 1 may be represented by the shortcode itself and each logical 0 may be represented by the inverted shortcode, or vice versa. The lengths of different shortcodes vary, e.g., from 16 chips to 128 chips.
After the spreading operation, the spread channels are combined to form a wideband CDMA-signal which is then transmitted via an air interface, e.g., from a base station of a CDMA telecommunications network to a receiving station.
Before transmission, the CDMA signal may be further processed using a so called longcode, e.g., to be able to reuse a set of shortcodes or to provide a higher level of data security. A longcode, similar to a short code, is constituted by a defined sequence of binary values or symbols, for example a pseudo-random sequence. The longcode may be processed with the combined channel data using, e.g., a XOR (Exclusive OR) operation. The receiving station may recover the original signal by using the identical longcode and a reverse logical operation.
In order to be readily available for processing, longcodes and shortcodes may be generated beforehand and stored in a memory device. However, storing a larger number of different short and/or longcodes requires large memories, which is expensive. Moreover, the memory devices need to be fast, in order to meet extremely high processing speeds in a telecommunications system. Further, different specialized pseudo-noise generators could be provided for generating different short and longcodes, e.g., needed for different system standards, but this is impractical, and alternative methods are sought.
It is therefore an object of the invention to provide a flexible sequence generator for generating different defined sequences of values.
The object of the invention is solved by an apparatus for generating sequences of values, comprising: a shift register having a plurality of register memory locations; selection means for selecting at least one register memory location as a feed-back location and at least one arbitrary register memory location as a feed-in location; processing means for processing output signals received from the at least one arbitrary register memory location selected as the feed-back location; and feeding means for feeding an output signal from the processing means to the at least one register memory location selected as the feed-in location.
Advantageously, at least one arbitrary shift register memory location may be selected as a feed-back location and at least one arbitrary shift register memory location may be selected as a feed-in location, and thus a plurality of different defined sequences of values can be generated, without changing a hardware configuration. The number of register memory locations active in generating a defined sequence of values may be set by selecting a first feed-in location, and the feed-back characteristic may be set by selecting at least one feed-back location. Accordingly, the sequence generator of the invention can be flexibly adapted to generate different defined sequences of discrete values and can thus be readily adapted, e.g., to system specifications.
First selection means may be provided for selectively connecting an output terminal of a register memory location to processing means, and second selection means may be provided for selectively connecting feeding means to a register memory location selected as a feed-in location. Advantageously, first and second selection means are controlled by control means.
Further, the processing means may include a plurality of processing units, for processing output signals of the at least one register memory location selected as the feed-back location, to form a signal to be fed to the at least one register memory location selected as the feed-in location. Advantageously, the processing means may perform a logical Exclusive OR (XOR) operation.
The object of the invention is further solved by an apparatus for generating sequences of values, comprising: a shift register having a plurality of register memory locations; selection means for selecting at least one register memory location as a feed-back location and at least one arbitrary register memory location as a feed-in location; processing means for processing output signals received from the at least one arbitrary register memory location selected as the feed-back location; feeding means for feeding an output signal from the processing means to the at least one register memory location selected as the feed-in location; wherein the selection means include data providing means for providing binary data for selecting the at least one feed-back register memory location and the at least one feed-in register memory location.
Advantageously, control means may include memory means or data providing means for storing or providing a bit sequence, the logical values of which being employed for defining the at least one feed-back location and the at least one feed-in location.
Further, the memory means may be provided with logic circuitry which controls the first and second selection means such that a first logical 1 of the bit sequence defines a feed-in location and each subsequent logical 1 defines a feed-back location, or such that a first logical 0 of the bit sequence defines a feed-in location and each subsequent logical 0 defines a feed-back location.
Further advantageous features of the invention are defined in further dependent claims.